A10-DATASHEET
2015.12.31
83
FPP Configuration Timing when DCLK-to-DATA[] = 1
Symbol
Parameter
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
DATA[]setup time before rising edge on DCLK
DATA[]hold time after rising edge on DCLK
DCLKhigh time
Minimum
Maximum
Unit
μs
μs
ns
ns
s
(96)
tCF2CK
3,010
—
—
(96)
tST2CK
tDSU
tDH
10
5.5
—
0
0.45 × 1/fMAX
0.45 × 1/fMAX
1/fMAX
—
tCH
—
tCL
DCLKlow time
—
s
tCLK
fMAX
tCD2UM
tCD2CU
DCLK period
—
s
DCLKfrequency (FPP ×8/×16/×32)
—
100
830
—
MHz
μs
—
(97)
CONF_DONEhigh to user mode
175
CONF_DONEhigh to CLKUSRenabled
4 × maximum DCLK
period
tCD2UMC
CONF_DONEhigh to user mode with CLKUSRoption on
tCD2CU
+
—
—
(600 × CLKUSR
period)
Related Information
FPP Configuration Timing
Provides the FPP configuration timing waveforms.
(95)
(96)
(97)
This value is applicable if you do not delay configuration by externally holding the nSTATUSlow.
If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.
The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
Arria 10 Device Datasheet
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