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10AX057H4F34I3LG 参数 Datasheet PDF下载

10AX057H4F34I3LG图片预览
型号: 10AX057H4F34I3LG
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 570000-Cell, CMOS, PBGA1152, 35 X 35 MM, ROHS COMPLIANT, FBGA-1152]
分类和应用: 可编程逻辑
文件页数/大小: 110 页 / 1391 K
品牌: INTEL [ INTEL ]
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A10-DATASHEET  
2015.12.31  
82  
FPP Configuration Timing when DCLK-to-DATA[] = 1  
Table 75: DCLK-to-DATA[] Ratio for Arria 10 Devices—Preliminary  
You cannot turn on encryption and compression at the same time for Arria 10 devices.  
Configuration Scheme  
Encryption  
Compression  
DCLK-to-DATA[] Ratio (r)  
Off  
Off  
Off  
On  
Off  
Off  
On  
Off  
Off  
On  
1
1
2
1
2
4
1
4
8
FPP (8-bit wide)  
On  
Off  
Off  
FPP (16-bit wide)  
FPP (32-bit wide)  
On  
Off  
Off  
On  
Off  
FPP Configuration Timing when DCLK-to-DATA[] = 1  
Note: When you enable decompression or the design security feature, the DCLK-to-DATA[]ratio varies for FPP ×8, FPP ×16, and FPP ×32. For the  
respective DCLK-to-DATA[]ratio, refer to the DCLK-to-DATA[]Ratio for Arria 10 Devices table.  
Table 76: FPP Timing Parameters When the DCLK-to-DATA[] Ratio is 1 for Arria 10 Devices—Preliminary  
Use these timing parameters when the decompression and design security features are disabled.  
Symbol  
Parameter  
nCONFIGlow to CONF_DONElow  
nCONFIGlow to nSTATUSlow  
nCONFIGlow pulse width  
Minimum  
Maximum  
600  
Unit  
ns  
tCF2CD  
tCF2ST0  
tCFG  
tSTATUS  
tCF2ST1  
2
600  
ns  
3,000 (94)  
3,000 (95)  
μs  
nSTATUSlow pulse width  
268  
μs  
nCONFIGhigh to nSTATUShigh  
μs  
(94)  
This value is applicable if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.  
Arria 10 Device Datasheet  
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Altera Corporation  
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