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10AX032E3F29I2SG 参数 Datasheet PDF下载

10AX032E3F29I2SG图片预览
型号: 10AX032E3F29I2SG
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 320000-Cell, CMOS, PBGA780, 29 X 29 MM, ROHS COMPLIANT, FBGA-780]
分类和应用: 可编程逻辑
文件页数/大小: 110 页 / 1391 K
品牌: INTEL [ INTEL ]
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A10-DATASHEET  
2015.12.31  
7
Transceiver Power Supply Operating Conditions  
Symbol  
Description  
Condition (12)  
Chip-to-Chip ≤ 17.4 Gbps  
Or  
Minimum (13)  
Typical  
Maximum  
Unit  
1.0  
1.03  
1.06  
V
Backplane (14) ≤ 16.0 Gbps  
VCCR_GXB[L,R]  
Receiver power supply  
Chip-to-Chip ≤ 11.3 Gbps  
Or  
0.92  
0.95  
1.8  
0.98  
V
V
Backplane (14) ≤ 10.3125 Gbps  
VCCH_GXB[L,R]  
Transceiver high voltage  
power  
1.710  
1.890  
Note: Most VCCR_GXB and VCCT_GXB pins associated with unused transceiver channels can be grounded on a per-side basis to minimize  
power consumption. Refer to the Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines and the Quartus Prime pin report for  
information about pinning out the package to minimize power consumption for your specific design.  
(12)  
(13)  
These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Arria 10 GX/SX Devices for exact data  
rate ranges.  
This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the  
PDN tool for the additional budget for the dynamic tolerance requirements.  
Arria 10 Device Datasheet  
Send Feedback  
Altera Corporation