A10-DATASHEET
2015.12.31
109
Document Revision History
Date
Version
Changes
August 2014
2014.08.18
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Changed the 3 V I/O conditions in Table 2.
Table 3:
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Added a note to the Minimum and Maximum operating conditions.
Changed VCCERAM values.
Changed the Maximum recommended operating conditions for 3 V I/O VI.
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Added a note to the I/O pin pull-up tolerance in Table 12.
Changed the VIH values for LVTTL, LVCMOS and 2.5 I/O standards in Table 13.
Table 14, Table 15, and Table 16:
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Added SSTL-12 I/O standard.
Removed Class I, II for SSTL-135 and SSTL-125 I/O standards.
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Table 19:
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Changed the minimum data rate specification for transmitter and receiver data rates.
Changed the minimum frequency specification for the fractional PLL.
Changed the minimum frequency specification for the CMU PLL.
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Changed the Core Speed Grade with Power Options section in Table 20.
Table 21:
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Changed the minimum data rate specification for transmitter and receiver data rates.
Changed the minimum frequency specification for the Fractional PLL.
Changed the minimum frequency specification for the CMU PLL.
Changed the minimum frequency of the ATX PLL.
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Table 23:
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Added a note to the High Speed Differential I/O standard.
Changed the specifications for CLKUSR pin.
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Added columns in Table 29.
Changed the maximum fHSCLK_in and txJitter in Table 32.
Changed the minimum formula for tCD2UMC in Table 42, Table 43, Table 44, and Table 46.
Changed the CLKUSR maximum frequency and minimum number of cycles in Table 47.
Arria 10 Device Datasheet
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