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10AS066K4F40E3SG 参数 Datasheet PDF下载

10AS066K4F40E3SG图片预览
型号: 10AS066K4F40E3SG
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 660000-Cell, CMOS, PBGA1517, 40 X 40 MM, ROHS COMPLIANT, FBGA-1517]
分类和应用: 可编程逻辑
文件页数/大小: 110 页 / 1391 K
品牌: INTEL [ INTEL ]
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A10-DATASHEET  
2015.12.31  
105  
Document Revision History  
Date  
Version  
Changes  
Updated the AS Timing Parameters for AS ×1 and AS ×4 Configurations in Arria 10 Devices table as  
follows:  
Changed the symbol for data hold time from tH to tDH  
Updated the minimum value for tSU from 0 ns to 1 ns.  
Updated the minimum value for tDH from 2.5 ns to 1.5 ns.  
.
Added a note to the DCLK Frequency Specification in the AS Configuration Scheme table. Note: You can  
only set 12.5, 25, 50, and 100 MHz in the Quartus Prime software.  
Added a note to the Initialization Clock Source Option and the Maximum Frequency for Arria 10 Devices.  
Note: If you use the CLKUSRpin for AS and transceiver calibration simultaneously, the only allowed  
frequency is 100 MHz.  
Changed Arria 10 GS to Arria 10 SX in Uncompressed .rbf Sizes and Minimum Configuration Time  
Estimation tables.  
Added IO_IN_DLY_CHN and IO_OUT_DLY_CHN in the IOE Programmable Delay table.  
Changed the Min/Typ/Max description for the VICM (AC coupled) parameter in the "Reference Clock  
Specifications" table.  
Changed the Min/Typ/Max values in the "Transceiver Power Supply Operating Conditions for Arria 10 GX/  
SX Devices" table.  
Changed the Min/Typ/Max values in the "Transceiver Power Supply Operating Conditions for Arria 10 GT  
Devices" table.  
Added a footnote to the maximum data rate for GT channels in the "Transceiver Performance for GT  
Devices" section.  
Made the following changes to the "Transceiver Performance for Arria 10 GX/SX Devices" section.  
Changed the maximum data rate condition for chip-to-chip and backplane in the "Transmitter and  
Receiver Data Rate Performance" table.  
Added TX minimum data rate to the "Transmitter and Receiver Data Rate Performance" table.  
Changed the minimum frequency in the "ATX PLL Performance" table.  
Changed the minimum frequency in the "Fractional PLL Performance" table.  
Changed the minimum and maximum frequency in the "CMU PLL Performance" table.  
Arria 10 Device Datasheet  
Send Feedback  
Altera Corporation  
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