IA82527
Data Sheet
CAN Serial Communications Controller
December 20, 2012
4.
Functional Description
4.1
Hardware Architecture
A block diagram of the IA82527 CAN Serial Communications Controller is shown in Figure 5.
The primary architectural features of the device are as follows:
• CAN Controller
• Message RAM
• CPU Interface
• I/O Ports
• Programmable Clock Output
These features are briefly described in the following subsections.
Mode
Select
clkout
Address/Data Bus
Control Bus
Programmable
Clock
rx0
rx1
Receive
{
{
Port 1 I/O
Port
1
CAN
Controller
CPU Interface
Internal
tx0
tx1
Transmit
Port 2 I/O
Port
2
Message
RAM
Registers
mosi
miso
Serial Interface
Figure 5. Functional Block Diagram
IA211080504-07
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