IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Preliminary Data Sheet
As of Production Version 00
Reset
A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator
periods) while the oscillator is running. The CPU responds by generating an internal reset, which is
executed during the second cycle in which RST is high.
The internal reset sequence writes ‘0’s to all SFRs except the port-latches, the Stack Pointer,
SIUST and unused bits of registers.
Reset Values
Register
PC
Reset value
0000H
ACC
B
PSW
SP
DPTR
P0 – P3
IP
00000000B
00000000B
00000000B
00000111B
0000H
11111111B
XXX00000B
0XX00000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
IE
TMOD
TCON
TH0
TL0
TH1
TL1
SMD
STS
NSNR
STAD
TBS
TBL
TCB
RBS
RBL
RFL
RCB
DMA CNT 00000000B
FIFO1
FIFO2
FIFO3
SIUST
00000000B
00000000B
00000000B
00000001B
Copyright
innovASIC
2001
ENG210010112-00
www.innovasic.com
Customer Support:
1-888-824-4184
The End of Obsolescence
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