IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Preliminary Data Sheet
As of Production Version 00
Timers/Counters
Timers 0 and 1
The C8051 has two 16-bit timer/counter registers: Timer 0 and Timer 1. Both can be configured
for counter or timer operations. In timer mode, the register is incremented every machine cycle,
which means that it counts up after every 12 oscillator periods. In counter mode, the register is
incremented when the falling edge is observed at the corresponding input pin T0 or T1. Since it
takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/24 of the
oscillator frequency. There are no restrictions on the duty cycle, however to ensure proper
recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle (12 clock
periods).
Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function
Registers (TMOD and TCON) are used to select the appropriate mode.
Copyright
innovASIC
2001
ENG210010112-00
www.innovasic.com
Customer Support:
1-888-824-4184
The End of Obsolescence
Page 14 of 32
INNOVASIC [ INNOVASIC, INC ]
