IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Preliminary Data Sheet
As of Production Version 00
Special Function Registers
The IA8044/IA8344 contains the following special function registers:
ACC
B
PSW
SP
Accumulator
B register *
program Status Word *
Stack Pointer
DPTR
P0
P1
Data Pointer (DPH and DPL)
Port 0 *
Port 1 *
P2
P3
Port 2 *
Port 3 *
IP
IE
Interrupt Priority *
Interrupt Enable *
Timer/Counter Mode
Timer/Counter Control *
Timer/Counter 0 high byte
Timer/Counter 0 low byte
Timer/Counter 1 high byte
Timer/Counter 1 low byte
Serial Mode
SIU Status and Command *
SIU Send/Receive Count *
SIU Station Address
Transmit Buffer Start Address
Transmit Buffer Length
Transmit Control Byte
Receive Buffer Start Address
Receive Buffer Length
Receive Field Length
Receive Control Byte
DMA Count
TMOD
TCON
TH0
TL0
TH1
TL1
SMD
STS
NSNR
STAD
TBS
TBL
TCB
RBS
RBL
RFL
RCB
DMA CNT
FIFO
SIUST
FIFO contents (3 bytes)
SIU State Counter
* - These registers are bit addressable.
Ports
Ports P0, P1, P2 and P3 are Special Function Registers. The contents of the SFR can be observed
on corresponding pins on the chip. Writing a ‘1’ to any of the ports causes the corresponding pin to
be at high level (VCC), and writing a ‘0’ causes the corresponding pin to be held at low level
(GND).
All four ports on the chip are bi-directional. Each of them consists of a Latch (SFR P0
to P3), an output driver, and an input buffer, so the CPU can output or read data through any
Copyright
innovASIC
2001
ENG210010112-00
www.innovasic.com
Customer Support:
1-888-824-4184
The End of Obsolescence
Page 12 of 32
INNOVASIC [ INNOVASIC, INC ]
