IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Preliminary Data Sheet
As of Production Version 00
Interrupt Handling
The interrupt flags are sampled during each machine cycle. The samples are polled
during the next machine cycle. If an interrupt flag is captured, the interrupt system will
generate an LCALL instruction to the appropriate service routine, provided that this is not
disabled by the following conditions:
1. An interrupt of the same or higher priority is processed
2. The current machine cycle is not the last cycle of the instruction (the instruction can
not be interrupted).
3. The instruction in progress is RETI or any write to IE or IP registers.
Note that if an interrupt is disabled and the interrupt flag is cleared before the blocking
condition is removed, no interrupt will be generated, since the polling cycle will not sample
any active interrupt condition. In other words, the interrupt condition is not remembered.
Every polling cycle is new.
SIU – Serial Interface Unit
The SIU is a serial interface customized to support SDLC/HDLC protocol. As such it supports
Zero Bit insertion/deletion, Flags automatic access recognition and a 16 bit CRC. The SIU has
two modes of operation AUTO and FLEXIBLE. The AUTO mode uses a subset of the SDLC
protocol implemented in hardware. This frees the CPU from having to respond to every frame but
limits the frame types. In the FLEXIBLE mode every frame is under CPU control and therefore
more options are available. The SIU is controlled by and communicates to the CPU by using
several special function registers (SFRs). Data transmitted to or received by the SIU is stored in
the 192 byte internal RAM in blocks referred to as the transmit and receive buffers. The SIU can
support operation in one of three serial data link configurations: 1) half-duplex, point-to-point, 2)
half-duplex, multipoint, 3) loop.
SIU Special Function Registers
The CPU controls the SIU and receives status from the SIU via eleven special function registers.
The Serial Interface Unit Control Registers are detailed below:
Copyright
innovASIC
2001
ENG210010112-00
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