IA6805E2
29 August 2007
Microprocessor Unit
As of Production Version 00
Description
The IA6805E2 (CMOS) Microprocessor Unit (MPU) is a low cost, low power MPU. It features a
CPU, on-chip RAM, parallel I/O compatibility with pins programmable as input or output. The
following paragraphs will further describe this system block diagram and design in more detail.
OSC1 OSC2
TIMER/
COUNTER
TIMER
PRESCALER
RESET_N
LI
TIMER CONTROL
OSCILLATOR
IRQ_N
PA0
B0
B1
B2
B3
B4
B5
B6
B7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
ACCUMULATOR
CPU
CONTROL
8
8
5
6
5
8
A
MULTIPLEXED
ADDRESS
DATA
MUX
BUS
DRIVE
PORT
A
I/O
INDEX
REGISTER
PORT
A
REG
DATA
DIR
REG
X
BUS
LINES
CONDITION
CODE
REGISTER
CC
SP
STACK
POINTER
CPU
PROGRAM
COUNTER
HIGH
A8
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PCH
A9
PROGRAM
COUNTER
LOW
ADDRESS
DRIVE
ADDRESS
BUS
A10
A11
A12
PORT
B
I/O
PCL
PORT
B
REG
DATA
DIR
REG
ALU
LINES
AS
ADDRESS STROBE
DATA STROBE
READ/WRITE
112x8
RAM
BUS
CONTROL
DS
RW_N
Figure 1. System Block Diagram
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IA211081401-03
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