IA6805E2
29 August 2007
Microprocessor Unit
As of Production Version 00
AS
n0
n1
n2
n3
n4
n5
n6
n7
n8
n9
DS
(NOTE)
TDSLIH
ADD_BUS_UNMUX[8:12]
1F (FF) 1F (FF)
NEXT OP CODE ADDRESS
INT ROUTINE
LAST ADDRESS
INT ROUTINE
STARTING ADDRESS
TILASL
IRQ_N__TCR7_N
SP-1
SP-2
SP-3
SP-4
NEW PCH
NEW PCL
MUX_ADD_DATA[0:7]
SP PCL
PCH
X
A
CC
80
NEXT OP CODE
FA (IRQ) FB (IRQ)
F8 (TIMER)F9 (TIMER) INT ROUTINE
1ST OP
RTI
OP CODE
RW_N
Note: tDSLIH- the interrupting device must release the IRQ_N line within this time to prevent subsequent recognition
of the same interrupt.
Figure 15. IRQ_n and TCR7_N Interrupt Timing
Figure 16. Power-On-Reset and RESET_n Timing
Copyright © 2007
IA211081401-03
www.Innovasic.com
Customer Support:
©
Page 27 of 33
1-888-824-4184
INNOVASIC [ INNOVASIC, INC ]
