IA6805E2
29 August 2007
Microprocessor Unit
As of Production Version 00
Opcode Map Summary:
The following table is an opcode map for the instructions used on the MPU. The legend
following the table shows how to use the table.
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
BTB
BSC
REL
DIR
3
INH
INH
IX1
IX
7
INH
INH
IMM
A
DIR
B
EXT
IX2
IX1
E
IX
F
0
1
2
4
5
6
8
9
C
D
Hi
Hi
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Low
Low
5
5
3
5
3
3
6
5
9
2
3
4
5
4
3
0
0 0000
1 0001
BRSET0
BSET0
BRA
NEG
NEGA
NEGX
NEG
NEG
RTI
SUB
SUB
SUB
SUB
SUB
SUB
CMP
SBC
CPX
0000
3
3
BTB 2
5
BSC 2
5
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX 1
INH
6
2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
1
BRCLR0
BCLR0
BRN
RTS
CMP
CMP
CMP
CMP
CMP
0001
BTB 2
5
BSC 2
5
REL
3
1
INH
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
2
2 0010
BRSET1
BSET1
BHI
SBC
SBC
SBC
SBC
SBC
0010
3
3
3
BTB 2
5
BSC 2
5
REL
3
2
2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
5
3
3
6
5
10
3
3 0011
4 0100
5 0101
BRCLR1
BCLR1
BLS
COM
COMA
COMX
COM
COM
LSR
SWI
INH
CPX
CPX
CPX
CPX
CPX
0011
BTB 2
5
BSC 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX 1
5
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
4
BRSET2
BSET2
BCC
LSR
DIR 1
LSRA
INH 1
LSRX
INH 2
LSR
IX1 1
AND
AND
AND
AND
AND
AND
IX
0100
BTB 2
5
BSC 2
5
REL 2
3
IX
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
3
5
BRCLR2
BCLR2
BCS
BIT
BIT
BIT
BIT
BIT
BIT
0101
3
3
BTB 2
5
BSC 2
5
REL
3
2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
5
3
3
6
5
6
6 0110
BRSET3
BSET3
BNE
ROR
RORA
RORX
ROR
ROR
ASR
LDA
LDA
LDA
LDA
LDA
LDA
STA
0110
BTB 2
5
BSC 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
IMM 2
DIR 3
4
EXT 3
5
IX2 2
6
IX1 1
5
IX
4
2
7
7 0111
8 1000
9 1001
A 1010
BRCLR3
BCLR3
BEQ
ASR
ASRA
ASRX
ASR
TAX
STA
STA
STA
STA
0111
3
3
3
BTB 2
5
BSC 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
1
1
1
INH
2
2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
8
BRSET4
BSET4
BHCC
LSL
LSLA
LSLX
LSL
LSL
CLC
EOR
EOR
EOR
EOR
EOR
EOR
ADC
1000
BTB 2
5
BSC 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
INH 2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
9
BRCLR4
BCLR4
BHCS
ROL
ROLA
ROLX
ROL
ROL
SEC
ADC
ADC
ADC
ADC
ADC
1001
BTB 2
5
BSC 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
INH 2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
A
1010
BRSET5
BSET5
BPL
DEC
DIR 1
DECA
INH 1
DECX
INH 2
DEC
IX1 1
DEC
CLI
ORA
ORA
ORA
ORA
ORA
ORA
3
BTB 2
5
BSC 2
5
REL 2
3
IX
1
INH 2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
B
1011
B 1011
C 1100
BRCLR5
BCLR5
BMI
SEI
ADD
ADD
ADD
ADD
ADD
ADD
IX
3
3
BTB 2
5
BRSET6
BSC 2
5
BSET6
REL
3
BMC
1
1
INH 2
2
IMM 2
DIR 3
2
JMP
EXT 3
3
JMP
IX2 2
4
JMP
IX1 1
3
JMP
5
3
3
6
5
2
C
1100
INC
INCA
INCX
INC
INC
TST
RSP
JMP
JSR
BTB 2
5
BSC 2
5
REL 2
3
DIR 1
4
INH 1
3
INH 2
3
IX1 1
6
IX
4
INH
2
2
6
DIR 3
5
EXT 3
6
IX2 2
7
IX1 1
6
IX
5
D
1101
D
1101
BRCLR6
BCLR6
BMS
TST
DIR 1
TSTA
INH 1
TSTX
INH 2
TST
IX1 1
NOP
BSR
JSR
JSR
JSR
JSR
3
3
3
BTB 2
5
BSC 2
5
REL 2
3
IX
1
INH 2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
2
E
1110
E 1110
F 1111
BRSET7
BSET7
BIL
STOP
LDX
LDX
LDX
LDX
LDX
LDX
BTB 2
5
BSC 2
5
REL
3
1
5
INH
2
2
2
IMM 2
DIR 3
4
EXT 3
5
IX2 2
6
IX1 1
5
IX
4
5
3
3
6
F
1111
BRCLR7
BTB 2
BCLR7
BSC 2
BIH
REL 2
CLR
DIR 1
CLRA
INH 1
CLRX
INH 2
CLR
CLR
WAIT
INH 1
TXA
INH
STX
STX
EXT 3
STX
IX2 2
STX
IX1 1
STX
IX1 1
IX 1
2
DIR 3
IX
REL
Relative
Bit set/clear
Bit test and branch
Indexed, no offset
Indexed, 1 byte offset
Indexed, 2 byte offset
Abbreviations for Address
Modes:
BSC
BTB
IX
IX1
IX2
Opcode in Hexadecimal
Opcode in Binary
F
1111
INH
A
X
IMM
DIR
EXT
Inherent
3
0
Mnemonic
Bytes
SUB
0000
Accumulator
Index Register
Immediate
Direct
IX
1
# of Cycles
Address Mode
Legend:
Extended
Copyright © 2007
IA211081401-03
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