IA6805E2
29 August 2007
Microprocessor Unit
As of Production Version 00
Bus Timing
VSS=0V, TA=TL to TH (Figure 19)
VDD = 5.0V ±10%
fOSC = 5MHz
1 TTL, 100pF Load
Num
Parameters
Unit
Min
1000
587
403
-
9
97
-
Max
DC
-
-
4
-
-
40
11
-
1
2
3
4
8
9
11
16
17
18
19
21
23
24
25
26
27
28
Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pulse Width, DS Low
Pulse Width, DS High
Clock Transition
RW_n
Non-Muxed Address Hold
RW_n Delay From DS Fall
Non-Muxed Address Delay From AS Rise
MPU Read Data Setup
Read Data Hold
-
18
0
MPU Data Delay, Write
Write Data Hold
-
0
-
26
-
-
-
204
-
Muxed Address Delay From AS Rise
Muxed Address Valid to AS Fall
Muxed Address Hold
Delay DS Fall to AS Rise
Pulse Width, AS High
Delay, AS Fall to DS Rise
185
103
190
203
185
-
-
VLOW = 0.8V, VHIGH = VDD – 2.0V, VDD = 5.0V ±10%
TA = TL to TH, CL on Port = 50pF, fOSC = 5MHz
*NOTE
ADDRESS_STROBE
PORT_INPUT
tPVASL
tASLPX
tASLPV
PORT_OUTPUT
*Note: The address strobe of the first cycle of the next instruction.
Figure 14. I/O Port Timing
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IA211081401-03
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