IA63484
Data Sheet
Advanced CRT Controller
Figure 16: Input Timing exsync_n
clk_2
tEXH
tEXSW
tEXS
exsync_n
tHSD
hsync_n
mcyc(phase_shifted)
mcyc(phase_not_shifted)
Figure 17: Input Timing (Single Access Mode) lpstb
Display_Cycle
clk_2
mcyc
tLPD1
mad[15:0]
lpstb
M
M+1
tLPH
M
tLPD2
Figure 18: Input Timing (Dual Access Mode) lpstb
Display_Cycle
clk_2
mcyc
mad[15:0]
M
M+1
M+2
tLPD1
tLPH
tLPD2
tLP1
lpstb
tLPD1
tLPH
tLPD2
tLP1
lpstb
Copyright ã 2001
innovASIC
ENG 21101041200
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