IA63484
Data Sheet
Advanced CRT Controller
AC Characteristics (continued):
Frame Memory Read / Write Cycle Timing:
9.8 MHz Version
Item
Symbol
Unit
Min
Max
tPWASL
tMAH2
tASD1
as_n "Low" Level Pulse Width
Memory Address Hold Time 2
as_n Delay Time 1
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
50
40
50
tASD2
as_n Delay Time 2
5
tMAD
Memory Address Delay Time
Memory Address Hold Time 1
Memory Address Turn Off Time (A to Z)
Memory Read Data Setup Time
Memory Read Data Hold Time
ma_ra Delay Time
10
15
tMAH1
tMAAZ
tMRDS
tMRDH
tMARAD
tMARAH
tMCYCD
tMRDD
tMRH
35
60
30
0
ma_ra Delay Time
5
5
MCYC Delay Time
40
50
mrd Delay Time
mrd Hold Time
5
5
draw_n Delay Time
tDRWD
tDRWH
tMWDD
tMWDH
tMAS1
50
50
draw_n Hold Time
Memory Write Data Delay Time
Memory Write Data Hold Time
Memory Address Setup Time 1
Memory Address Setup Time 2
5
10
10
tMAS2
NOTE: t MAD is independent of clk_2 operation frequency (f) and timing of tASD2 and t MAS1
Copyright ã 2001
innovASIC
ENG 21101041200
Page 26 of 32
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