IA63484
Data Sheet
Advanced CRT Controller
Figure 12: DMA Write Cycle Timing
clk_2
tDRQD1
dreq_n
rw_n
tDRQD2
tDAKS
tDMRWS
tDMRWH
dack_n
d[15:0]
tDWDS tDWDH
tDWW
tDDTLH
tDNLZ1
tDDTZL
dtack_n_ready_n
done_n(output)
done_n(input)
tDDTHZ
tDND
tDNPW
Figure 13: Display Cycle Timing
refresh_cycle
tASD2
attribute_cntl_info_out_cycle
clk_2
as_n
tPWASL
tASD1
tMAA2
tMAH1
tATRD1
tATRH1
tMAS1
tMAD
refresh_adrs
refresh_adrs ATR
mad[15:0
]
tATRH2
tATRD2
ATR
tMARAD
tMCYCD
tMRDD
tDRWD
ma19_16_ra[3:0]
mcyc
mrd
tMRH
tDRWH
draw_n
Copyright ã 2001
innovASIC
ENG 21101041200
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