IA63484
Data Sheet
Advanced CRT Controller
Figure 14: Frame Memory Refresh & Video Attributes Output Cycle Timing
Refresh_cycle
Attribute_cntl_info_out_cycle
clk_2
tASD2
tASD1
tPWASL
as_n
tMAA2 tMAS1
tMAH1
tATRH1
tATRD1
tMAD
refresh_adrs
mad[15:0]
refresh_adrs
ATR
tATRH2
tMARAD
tMCYCD
tMRDD
tDRWD
tHSD
tATRD2
ma19_16_ra[3:0]
mcyc
ATR
tMRH
tDRWH
tHSD
mrd
draw_n
hsync_n
Figure 15: Display Control Signal Output Timing
clk_2
tMCYD
mcyc
tHSD
tVSD
hsync_n_vsync_n
tDSPD
disp1_n_disp2_n
tCUDD
cud1_n_cud2_n
tEXD
exsync_n
tCHD
chr
Copyright ã 2001
innovASIC
ENG 21101041200
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