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IA21140AF-PQF144I 参数 Datasheet PDF下载

IA21140AF-PQF144I图片预览
型号: IA21140AF-PQF144I
PDF下载: 下载PDF文件 查看货源
内容描述: PCI快速以太网控制器 [PCI FAST ETHERNET LAN CONTROLLER]
分类和应用: 外围集成电路控制器PC局域网以太网以太网:16GBASE-T
文件页数/大小: 19 页 / 97 K
品牌: INNOVASIC [ INNOVASIC, INC ]
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IA21140AF  
Preliminary Data Sheet  
PCI FAST ETHERNET LAN CONTROLLER  
NAME  
Type  
Description  
serr_n  
O/D  
Reports errors other than parity. Signal must be valid for at least one clock  
cycle. This pin pulled up by an external resistor.  
Serial ROM clock.  
sr_ck  
sr_cs  
sr_di  
O
O
O
I
Serial ROM chip-select pin pulled down by an internal 2 k O resistor.  
Serial ROM data-in.  
sr_do  
Serial ROM data-out pin pulled up by an internal 5 k O resistor.  
srl_clsn  
I
Indicates a collision occurrence on the Ethernet cable to the IA21140AF.  
Asserted and deasserted asynchronously by the external ENDEC with  
respect to the receive clock.  
srl_rclk  
srl_rxd  
srl_rxen  
I
I
I
Carries the recovered receive clock supplied by an external ENDEC. May be  
inactive during idle periods.  
Carries the input receive data from the external ENDEC. Incoming data  
should be synchronous with receive clock (srl_rclk) signal.  
Set when receive data is present on the Ethernet cable and cleared at the  
end of a frame. Set and cleared asynchronously to the receive clock by the  
external ENDEC.  
srl_tclk  
srl_txd  
I
Carries the transmit clock supplied by an external ENDEC. Must be always  
active, even during reset.  
O
Carries the serial output data from the IA21140AF and is synchronized to  
transmit clock signal.  
srl_txen  
stop_n  
O
Signals an external ENDEC that the IA21140AF transmit is in progress.  
I/O  
The current target is requesting the bus master to stop the current  
transaction.  
sym_link  
O
I
Descrambler is locked to the input data signal.  
sym_rxd[4]  
This signal and the four receive lines mii_sym_rxd[3:0], provide five parallel  
data lines in symbol form for use in PCS mode. Data is driven by an external  
PMD device and is synchronized with respect to the mii_sym_rclk signal.  
sym_txd[4]  
O
This signal and the four transmit lines mii_sym_txd[3:0], provide five parallel  
data lines in symbol form for use in PCS mode. Data is synchronized on the  
rising edge of mii_sym_tclk.  
tck  
Tdi  
I
I
During JTAG test operations this clock shifts state information and test data  
into and out of the IA21140AF. The pin should not be left unconnected.  
During JTAG test operations this pin serially shifts test data and instruction  
into the IA21140AF. The pin is pulled up by an internal 5 k O resistor and  
should not be left unconnected.  
tdo  
O
I
During JTAG test operations this pin serially shifts test data and instructions  
out of the IA21140AF.  
tms  
Controls the state operation of JTAG testing in the IA21140AF. The pin is  
pulled up by an internal 5 k O resistor and should not be left unconnected.  
trdy_n  
I/O  
Indicates the readiness of the target’s agent to complete the current data  
phase of the transaction. During reads, this signal indicates that valid data is  
present on AD lines. During writes, this signal indicates the target is ready to  
accept data. A data phase is completed on any clock when both irdy_n and  
trdy_n are set.  
Copyright 2001  
innovASIC  
ENG210010110-00  
www.innovasic.com  
Customer Support:  
The End of Obsolescence  
Page 7 of 19  
1-888-824-4184