IA21140AF
Preliminary Data Sheet
PCI FAST ETHERNET LAN CONTROLLER
Description
The innovASIC IA21140AF Fast Ethernet LAN controller provides a direct interface connection to
the PCI (Peripheral Component Interface) bus. It interfaces with the PCI bus by using on-chip
control and status registers (CSR’s), and a shared CPU memory area. The memory is initialized once
during setup to minimize CPU overhead during normal operation. Large receive and transmit
FIFO’s are contained on-chip so no additional on board memory is required. The IA21140AF
includes two on chip direct memory access (DMA) controllers with programmable burst size
providing for low CPU utilization. A PCI clock frequency from dc to 33 MHz (20-33 MHz for
operational network interface) is supported. Two network ports are supported. A serial standard 7-
wire 10-Mbps port (SRL) and a media independent interface/symbol 10/100-Mbps port
(MII/SYM). The 10 Mbps implements a direct interface to the external 10 Mbps front-end decoder
(ENDEC). The 10/100 Mbps port supports two modes. The first is a 100BASE-X physical coding
sublayer (PCS). The second is a full implementation of the MII standard. The IA21140AF functions
in a full-duplex environment for either network port.
Copyright 2001
innovASIC
ENG210010110-00
www.innovasic.com
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