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IA21140AF-PQF144I 参数 Datasheet PDF下载

IA21140AF-PQF144I图片预览
型号: IA21140AF-PQF144I
PDF下载: 下载PDF文件 查看货源
内容描述: PCI快速以太网控制器 [PCI FAST ETHERNET LAN CONTROLLER]
分类和应用: 外围集成电路控制器PC局域网以太网以太网:16GBASE-T
文件页数/大小: 19 页 / 97 K
品牌: INNOVASIC [ INNOVASIC, INC ]
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IA21140AF  
Preliminary Data Sheet  
PCI FAST ETHERNET LAN CONTROLLER  
I/O Description  
The following section provides a functional description of the I/O pins on the IA21140AF.  
NAME  
Type  
Description  
Vdd  
P
3.3 volt input supply voltage.  
Vdd_clamp  
P
5.0 volt reference for 5.0 volt signaling environments and 3.3 volt reference  
for 3.3 volt signaling environments.  
Vss  
P
Ground Pin  
ad[31:0]  
I/O  
The PCI address and data lines are multiplexed on the same PCI pins. During  
the first clock cycle of a transaction, the 32 bits contain an address and during  
subsequent clock cycles, they contain data. Both read and write bursts are  
supported in master operation only. Big or Little Indian byte ordering can be  
used.  
br_a[1:0]  
O
Address line bit 0 also carries in two consecutive address cycles (bits 16 and  
17) in a 256KB configuration. Bit 1 also latches the boot ROM address and  
control lines via two external latches.  
br_ad[7:0]  
I/O  
In the first of two consecutive address cycles, these multiplexed lines contain  
the boot ROM address bits [7:2], oe_n, and we_n. The second cycle contains  
boot ROM address bits [15:8]. Bits 7 through 0 contain data during the data  
cycle. These lines are used to carry data to and from the external register.  
br_ce_n  
O
Enable pin for the Boot ROM or an external register. Pin has an internal 5 k O  
pull-up resistor.  
c_be_n[3:0]  
I/O  
Bus command and byte enable are multiplexed on the same PCI pins. These  
bits provide the bus command during the address phase of the transaction.  
They provide the byte enable during the data phase. Byte enable determines  
which byte lines carry valid data. Bit 0 coincides with byte 0. Bit 1 coincides  
with byte 1, etc.  
devsel_n  
frame_n  
I/O  
I/O  
Indicates that the driving device has decoded its address as the target of the  
current access. As an input, determines whether a device on the bus has  
been selected.  
The IA21140AF bus master asserts this signal to indicate the beginning and  
duration of a bus transaction access. Data transfer continues while this signal  
is asserted. Deasserting this signal indicates the transaction is in the final  
phase.  
gep[7:0]  
I/O  
These pins can be configured by software to perform either input or output  
functions for system specific applications.  
gnt_n  
Idsel  
I
I
Indicates to the IA21140AF that access to the bus has been granted.  
Used as a chip select by the host to indicate configuration read and write  
cycles.  
int_n  
O/D  
When one of the appropriate bits in CSR5 gets set, interrupt request gets  
asserted if the corresponding mask bit in CSR7 is not set. If more than one  
interrupt bit in CSR5 is set and all input bits are not cleared, interrupt request  
gets deasserted for one clock cycle. Interrupt request gets deasserted by  
writing a “1” into the appropriate CSR5 bit. This pin must be pulled up by an  
external resistor.  
Copyright 2001  
innovASIC  
ENG210010110-00  
www.innovasic.com  
Customer Support:  
The End of Obsolescence  
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