IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
4.
Device Architecture
A functional block diagram of the IA186ER/IA188ER is shown in Figure 7. This
microcontroller consists of the following functional blocks.
Bus Interface and Control (BIC)
32 Kbytes RAM
Peripheral Control and Registers
Chip Selects and Control (CSC)
Programmable I/O
Clock and Power Management
DMA
Interrupt Controller
Timers
Asynchronous Serial Port
Synchronous Serial Interface
Watchdog Timer
Instruction Decode and Execution
4.1
Bus Interface and Control
BIC manages all accesses to external memory, external peripherals and the internal 32 Kbyte
RAM. These peripherals may be mapped either in memory space or I/O space. The BIC
supports both multiplexed and non-multiplexed bus operations. Multiplexed address and data
are provided on the ad15–ad0 bus, while a non-multiplexed address is provided on the a19–a0
bus. The a bus provides address information for the entire bus cycle (t1–t4), while the ad bus
provides address information only during the first phase of the bus cycle (t1). For more details
regarding bus cycles, see the AC waveforms at the end of this datasheet.
The IA186ER microcontroller provides two signals that serve as byte write enables, write high
byte (whb_n) and write low byte (wlb_n). The IA188ER microcontroller requires only a single
write byte (wb_n) signal to support its 8-bit data bus. The whb_n is the logical OR of the bhe_n
and wr_n. The wlb_n is the logical OR of ad0 and wr_n. The wb_n is low whenever a byte is
written to the IA188ER data bus ad7–ad0.
The byte write enables are driven in conjunction with the non-multiplexed address bus a19–a0 to
support the timing requirements of common SRAMs.
The BIC also provides support for PSRAM devices. PSRAM is supported in only the lower chip
select (lcs_n) area. In order to support PSRAM, the CSC must be appropriately programmed
(see Section 4.7, Chip Selects).
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