IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
2.2.41 tmrout0/pio10—Timer Output 0 (synchronous output)
This signal provides the system with a single pulse or a continuous waveform with a
programmable duty cycle. It is tristated during a bus hold or reset.
2.2.42 tmrout1/pio1—Timer Output 1 (synchronous output)
This signal provides the system with a single pulse or a continuous waveform with a
programmable duty cycle. It is tristated during a bus hold or reset.
2.2.43 txd/pio27—Transmit Data (asynchronous output)
This pin provides the system with asynchronous serial transmit data from the serial port.
2.2.44 ucs_n/once1_n—Upper Memory Chip Select (synchronous output)/ONCE Mode
Request 1 (input with internal pull-up)
The ucs_n pin provides an indication that a memory access is in progress to the upper memory
block. The size of the Upper Memory Block and its base address are programmable, with the
size adjustable up to 512 Kbytes. The ucs_n pin is held high during bus hold.
After power-on-reset, ucs_n is asserted low and program execution begins at FFFF0h. Its default
configuration is a 64-Kbyte memory range from F0000h to FFFFFh.
The once0_n pin (ONCE – ON Circuit Emulation) and its companion pin, once1_n, define the
microcontroller mode during reset. These two pins are sampled on the rising edge of res_n and if
both are asserted low the microcontroller starts in ONCE mode, else it starts normally. In ONCE
mode, all pins are tristated and remain so until a subsequent reset. To prevent the
microcontroller from entering ONCE mode inadvertently, this pin has a weak pull-up that is only
present during reset. This pin is not tristated during bus hold.
2.2.45 uzi_n/clksel2_n/pio26—Upper Zero Indicate (synchronous output)/clock select 2
(input, pullup)
This pin allows the designer to determine if an access to the interrupt vector table is in progress
by ORing it with Bits [15–10] of the address and data bus (ad15–ad10 on the IA186ER and
ao15–ao10 on the IA188ER). The uzi_n is the logical OR of the inverted a19–a16 bits. It asserts
in the first period of a bus cycle and is held throughout the cycle.
clksel2_n is combined with s6/clksel1_n/pio29 to select clock mode. If low, part enters clock
mode x1. Default, because of pull-ups, is for x4 clock mode. This is sampled on the rise of reset.
2.2.46 vcc—Power Supply (input)
These pins supply power (+3.3V +10%) to the microcontroller.
IA211110517-02
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