IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
2.2.33 s0_n, s1_n (imdis_n), s0_n (sren_n) —Bus Cycle Status (synchronous outputs
with tristate)
These three signals inform the system of the type of bus cycle in progress. The s2_n may be
used to indicate whether the current access is to memory or I/O, and s1_n may be used to
indicate whether data is being transmitted or received. These signals are tristated during bus
hold and hold acknowledge. The coding for these pins is presented in Table 10.
imdis_n: Internal Memory Disable (input, pullup); if low during reset, internal memory is
disabled.
sren_n: Show Read Enable (input, pullup); if low during reset, reads from internal memory are
driven on the external address/data bus.
Table 10. Bus Cycle Types for s2_n, s1_n, and s0_n
s2_n s1_n s0_n Bus Cycle
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt acknowledge
Read data from I/O
Write data to I/O
Halt
Instruction fetch
Read data from memory
Write data to memory
None (passive)
2.2.34 s6/clksel1_n/pio29—Bus Cycle Status Bit 6 (synchronous output)/Clock Divide
by 2 (input with internal pull-up)
The s6 signal is high during the second and remaining cycle periods (i.e., t2 – t4), indicating that a
DMA-initiated bus cycle is underway. The s6 is tristated during bus hold or reset.
Combined with uzi_n/clksel2_n to select clock mode. If low, input clock is divided by two and
the PLL is disabled. Default, because of pull-ups, is for x4 clock mode. This pin is sampled on
the rise of reset.
Note: If this pin is used as pio29 and configured as an input, care should be
taken that it is not driven low during POR.
Because this pin has an internal pull-up, it is not necessary to drive the pin high even though it
defaults to an input PIO.
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