IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
interrupt controller. Before this can occur, however, the int0 pin must have already indicated an
interrupt request.
2.2.18 int2/inta0_n/pio31—Maskable Interrupt Request 2 (asynchronous input)/Interrupt
Acknowledge 0 (synchronous output)
The int2 pin provides an indication that an interrupt request has occurred, and provided that int2
is not masked, program execution will continue at the location specified by the int2 vector in the
interrupt vector table. Although interrupt requests are asynchronous, they are synchronized
internally and may be edge- or level-triggered. To ensure that it is recognized, the assertion of
the interrupt request must be maintained until it is handled. When int0 is configured for cascade
mode, int2 changes its function to inta0_n.
The inta0_n function indicates to the system that the microcontroller requires an interrupt type in
response to the interrupt request int0 when the microcontroller’s Interrupt Control Unit is in
cascade mode. The peripheral device that issued the interrupt must provide the interrupt type.
2.2.19 int3/inta1_n/irq—Maskable Interrupt Request 3 (asynchronous input)/Interrupt
Acknowledge 1 (synchronous output)/Interrupt Request (synchronous output)
The int3 pin provides an indication that an interrupt request has occurred. If int3 is not masked,
program execution will continue at the location specified by the int3 vector in the interrupt
vector table. Although interrupt requests are asynchronous, they are synchronized internally and
may be edge- or level-triggered. To ensure that it is recognized, the assertion of the interrupt
request must be maintained until it is handled. When int1 is configured to be in cascade mode,
int3 changes its function to inta1_n.
The inta1_n function indicates to the system that the microcontroller requires an interrupt type in
response to the interrupt request int1 when the microcontroller’s Interrupt Control Unit is in
cascade mode. The peripheral device that issued the interrupt must provide the interrupt type.
Irq allows the microcontroller to output an interrupt request to the external master interrupt
controller when the Interrupt Control Unit of the microcontroller is in slave mode.
2.2.20 int4/pio30—Maskable Interrupt Request 4 (asynchronous input)
The int4 pin provides an indication that an interrupt request has occurred, and provided that int4
is not masked, program execution will continue at the location specified by the int4 vector in the
interrupt vector table. Although interrupt requests are asynchronous, they are synchronized
internally and may be edge- or level-triggered. To ensure that it is recognized, the assertion of
the interrupt request must be maintained until it is handled.
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