IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Table 87. PSRAM Read Cycle Timing
a
a
No.
Name
Comment
Min
Max
General Timing Requirements
1
2
tDVCL
tCLDX
Data in Setup
Data in Hold
6.6
2
–
–
General Timing Responses
5
tCLAV
tCLDV
tCHDX
tCHLH
tLHLL
tCHLL
tLHAV
ad Address Valid Delay
Data Valid Delay
Status Hold Time
ale Active Delay
0
10
10
–
7
0
8
0
9
0
10
–
10
11
23
80
81
84
ale Width
15
ale Inactive Delay
ale High to Address Valid
0
10
–
7.5
tCLCLX lcs_n Inactive Delay
tCLCSL lcs_n Active Delay
0
10
10
–
0
tLRLL
lcs_n Precharge Pulse Width
tCLCL+ tCLCH
Read Cycle Timing Responses
24
25
26
27
28
59
66
68
tAZRL
tCLRL
tRLRH
tCLRH
tRHLH
tRHDX
tAVRL
tCHAV
ad Address Float to rd_n Active
rd_n Active Delay
0
–
10
–
0
rd_n Pulse Width
35
rd_n Inactive Delay
0
10
–
rd_n Inactive to ale High
rd_n High to Data Hold on ad Bus
a Address Valid to rd_n Low
clkouta High to a Address Valid
tCLCH
0
30
0
–
–
10
a
In nanoseconds.
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