IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Table 82. AC Characteristics Over Industrial Operating Ranges (50 MHz) (Continued)
No.
Name
Description
Mina
Maxa
Read Cycle Timing Responses
24 tAZRL
25 tCLRL
26 tRLRH
27 tCLRH
28 tRHLH
29 tRHAV
30 tCLDOX
ad Address Float to rd_n Active
rd_n Active Delay
rd_n Pulse Width
0
0
–
10
–
10
–
tCLCL
0
tCLCH
tCLCL
0
rd_n Inactive Delay
rd_n Inactive to ale High
rd_n Inactive to ad Address Active
Data Hold Time
–
–
Write Cycle Timing Responses
31 tCVCTX
32 tWLWH
33 tWHLH
34 tWHDX
Control Inactive Delay
wr_n Pulse Width
wr_n Inactive to ale High
Data Hold after wr_n
0
2tCLCL
tCLCH
10
–
–
–
tCLCL
35 tWHDEX wr_n Inactive to den_n Inactive
tCLCH
–
41 tDSHLH
59 tRHDX
65 tAVWL
66 tAVRL
67 tCHCSV
68 tCHAV
87 tAVBL
ds_n Inactive to ale Inactive
tCLCH
–
–
–
–
10
rd_n High to Data Hold on ad Bus
a Address Valid to wr_n Low
a Address Valid to rd_n Low
clkouta High to lcs_n/usc_n Valid
clkouta High to a Address Valid
a Address Valid to whb_n/wlb_n Low
0
tCLCL + tCHCL
tCLCL + tCHCL
0
0
10
tCHCL
tCHCL -1.5
Refresh Timing Cycle Parameters
79 tCHRFD
82 tCLRF
85 tRFCY
86 tLCRF
clkouta High to rfsh_n Valid
clkouta High to rfsh_n Invalid
rfsh_n Cycle Time
0
0
12
12
–
6tCLCL
2tCLCL
lcs_n Inactive to rfsh_n Active Delay
–
clkin Timing (Times Four Mode)
36 tCKIN
37 tCLCK
38 tCHCK
39 tCKHL
40 tCKLH
x1 Period
80
35
35
–
125
–
–
5
5
x1 Low Time
x1 High Time
x1 Fall Time
x1 Rise time
–
clkout Timing (Times Four Mode)
42 tCLCL
43 tCLCH
44 tCHCL
clkouta Period
clkouta Low Time
clkouta High Time
20
9
9
–
–
–
45 tCH1CH2 clkouta Rise Time
–
3
46 tCL2CL1
61 tLOCK
69 tCICOA
70 tCICOB
clkouta Fall Time
–
–
–
–
3
Maximum PLL Lock Time
x1 to clkouta Skew
x1 to clkoutb Skew
1 ms
15
21
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