IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Bits [15–3]—Reserved.
Bit [2]—RE/TE Receive/Transmit Error Detect → This bit is set to 1 when a read of the
Synchronous Serial Received register or a write to one of the transmit register is detected
while the interface is busy (PB = 1). This bit is reset to 0 when the SDEN output is not
active (DE1–DE0 in the SSC register are 00h).
Bit [1]—DR/DT Data Receive/Transmit Complete → This bit is set to a 1 when the
transmission of data Bit [7] is completed (SCLK rising edge) during a transmit or receive
operation. This bit is reset by a read of the SSR register, when either the SSD0 or SSD1
register is written, when the SSS register is read (unless the SSI completes an operation
and sets the bit in the same cycle), or when both SDEN0 and SDEN1 become inactive.
Bit [0]—PB SSI Port Busy → This bit indicates that a data transmit or receive is
occurring when it is set to 1. When set to 0, it indicates that the port is ready to transmit
or receive data.
5.2
Reference Documents
Additional information on the operation and programming of the IA186ER/ IA188ER can be
found in the following Advanced Micro Devices (AMD) publications:
Am186 ER and Am188 ER Microcontrollers User’s Manual, March 1998, Publication
21684, Rev B, Amendment/1.
Am186 ER and Am188 ER Data Sheet, June 2000, Publication 20732, Rev. D,
Amendment 0.
6.
AC Specifications
Table 82 presents the AC characteristics over industrial operating ranges (50 MHz). Tables 83
and 84 present the alphabetic and numeric keys to waveform parameters, respectively. Figure 11
presents the read cycle. Figure 12 presents the multiple read cycles. Table 85 presents the read
cycle timing. Figure 13 presents the write cycle. Figure 14 presents the multiple write cycles.
Table 86 presents the write cycle timing.
Figure 15 presents the PSRAM read cycle. Table 87 presents the PSRAM read cycle timing.
Figure 16 presents the PSRAM write cycle. Table 88 presents the PSRAM write cycle timing.
Figure 17 presents the PSRAM refresh cycle. Table 89 presents the PSRAM refresh cycle
timing. Figure 18 presents the interrupt acknowledge cycle. Table 90 presents the interrupt
acknowledge cycle timing. Figure 19 presents the software halt cycle. Table 91 presents the
software halt cycle timing. Figure 20 presents the clock—active mode. Figure 21 presents the
clock—power-save mode. Table 92 presents the clock timing.
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