IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Table 83. Alphabetic Key to Waveform Parameters (Continued)
No. Name
Description
7
2
tCLDV
tCLDX
tCLEV
tCLHAV
tCLRF
tCLRH
tCLRL
tCLSH
tCLSL
tCLSRY
tCLTMV
tCOAOB
tCVCTV
tCVCTX
tCVDEX
tCXCSX
tDVCL
tDVSH
tDXDL
tHVCL
tINVCH
tINVCL
tLCRF
Data Valid Delay
Data in Hold
clkouta Low to sden Valid
hlda Valid Delay
clkouta High to rfsh_n Invalid
rd_n Inactive Delay
71
62
82
27
25
4
72
48
55
83
20
31
21
17
1
75
19
58
53
54
86
23
10
13
61
84
57
85
29
59
28
26
77
78
47
35
34
33
32
rd_n Active Delay
Status Inactive Delay
clkouta Low to sclk Low
srdy Transition Hold Time
Timer Output Delay
clkouta to clkoutb Skew
Control Active Delay 1
Control Inactive Delay
den_n Inactive Delay
mcs_n/pcs_n Hold from Command Inactive
Data in Setup
Data Valid to SCLK High
den_n Inactive to dt/r_n Low
hld Setup Time
Peripheral Setup Time
drq Setup Time
lcs_n Inactive to rfsh_n Active Delay
ale High to Address Valid
ale Width
ad Address Hold from ALE Inactive
Maximum PLL Lock Time
lcs_n Precharge Pulse Width
res_n Setup Time
tLHAV
tLHLL
tLLAX
tLOCK
tLRLL
tRESIN
tRFCY
tRHAV
tRHDX
tRHLH
tRLRH
tSHDX
tSLDV
tSRYCL
tWHDEX
tWHDX
tWHLH
tWLWH
rfsh_n Cycle Time
rd_n Inactive to ad Address Active
rd_n High to Data Hold on ad Bus
rd_n Inactive to ale High
rd_n Pulse Width
sclk High to SPI Data Hold
sclk Low SPI Data Hold
srdy Transition Setup Time
wr_n Inactive to den_n Inactive
Data Hold after wr_n
wr_n Inactive to ale High
wr_n Pulse Width
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