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IA16450
Preliminary Data Sheet
Universal Asynchronous Receiver/Transmitter
Name
RI_n
Type
Description
I
Ring Indicator - Active Low - Active state indicates that the ring
signal has been detected by the MODEM or data set. A change
in state of this input is recorded in the TERI bit (bit 2) of the
MODEM Status register. Whenever DSR_n changes state, an
interrupt is generated if the MODEM Status interrupt is
enabled. The complement of this input is recorded in the RI
(bit 6) bit of the MODEM Status register
DOUT(7:0)
DDIS
O
O
Data Output Bus - Active high - Serves as output data when
reading from internal UART registers.
Driver Disable - Active High - Active State indicates that the
CPU is reading data from the UART. This output is intended as
a disable or direction control between the UART and CPU.
CSOUT
O
Chip Select Output - Active High - Active State indicates that
the megafunction has been selected by use of the CS0, CS1 and
CS2_n inputs.
SOUT
O
O
Serial Data Out - Active High - Serial (transmit) data out. This
signal is set to the marking (logic 1) state upon master reset.
BAUDOUT_n
Baud Out - Active Low - The 16x baud rate clock used by the
transmitter section of the UART. This output is controlled by
the programmable baud rate generator.
RTS_n
O
O
Request to Send - Active Low - This output indicates that the
UART is ready to exchange data. This output is controlled by
writing to the RTS (bit 1) bit of the control register.
DTR_n
Data Terminal Ready - Active Low - This output indicates that
the UART is ready to establish a communications link. This
output is controlled by writing to the DTR (bit 0) bit of the
control register.
OUT1_n
OUT2_n
INTR
O
O
O
Discrete Output - Active Low - One of two user-programmable
discrete outputs. This output is controlled by writing to the
OUT1 (bit 2) bit of the control register.
Discrete Output - Active Low - One of two user-programmable
discrete outputs. This output is controlled by writing to the
OUT2 (bit 3) bit of the control register.
Interrupt - Active High - Indicates that an enabled interrupt has
had its interrupt condition met.
Copyright ã 1999, InnovASIC Inc.
Customer Specific IC Solutions
INNOVASIC [ INNOVASIC, INC ]
