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IA16450-PLC44C 参数 Datasheet PDF下载

IA16450-PLC44C图片预览
型号: IA16450-PLC44C
PDF下载: 下载PDF文件 查看货源
内容描述: 通用异步接收器/发送器 [Universal Asynchronous Receiver/Transmitter]
分类和应用:
文件页数/大小: 10 页 / 100 K
品牌: INNOVASIC [ INNOVASIC, INC ]
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Page 4 of 10  
IA16450  
Preliminary Data Sheet  
Universal Asynchronous Receiver/Transmitter  
Name  
RD_n  
Type  
Description  
I
Read Control - Active low - when RD is high or RD_n is low  
and the UART is selected, read transactions from internal  
UART registers are possible.  
WR  
I
I
Write Control - Active High - when WR is high or WR_n is low  
and the UART is selected, write transactions to internal UART  
registers are possible.  
WR_n  
Write Control - Active low - when WR is high or WR_n is low  
and the UART is selected, write transactions to internal UART  
registers are possible.  
SIN  
I
I
Serial Data Input - Active High - Receive data to the UART  
RCLK  
Receive Clock - The 16x baud rate clock used by the receiver  
section of the UART.  
CTS_n  
I
Clear To Send - Active Low - Active state indicates that the  
MODEM or data set is ready to exchange data. A change in  
state of this input is recorded in the DCTS bit (bit 0) of the  
MODEM Status register. Whenever CTS_n changes state, an  
interrupt is generated if the MODEM Status interrupt is  
enabled. The complement of this input is recorded in the CTS  
(bit 4) bit of the MODEM Status register  
DSR_n  
I
Data Set Ready - Active Low - Active state indicates that the  
MODEM or data set is ready to establish the communications  
link with the UART. A change in state of this input is recorded  
in the DDSR bit (bit 1) of the MODEM Status register.  
Whenever DSR_n changes state, an interrupt is generated if the  
MODEM Status interrupt is enabled. The complement of this  
input is recorded in the DSR (bit 5) bit of the MODEM Status  
register  
DCD_n  
I
Data Carrier Detect - Active Low - Active state indicates that  
the data carrier has been detected by the MODEM or data set.  
A change in state of this input is recorded in the DDCD bit (bit  
3) of the MODEM Status register. Whenever DCD_n changes  
state, an interrupt is generated if the MODEM Status interrupt  
is enabled. The complement of this input is recorded in the  
DCD (bit 7) bit of the MODEM Status register  
Copyright ã 1999, InnovASIC Inc.  
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