fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
The Port 1 Link/Neighbor Status Receive Source ID register is comprised of three 16- bit
registers. It contains the source MAC address of the last Link/Neighbor Status frame that
was received on port 1. Reads may be performed in any order.
9.2.32 Port 2 Link/Neighbor Status Receive Source ID Register
Mnemonic
type offset bits 15
0x8E
14
13
12
11
10
9
8
7
6
5
4
0
4
3
0
3
0
3
0
2
0
2
0
2
0
1
0
1
0
1
0
0
0
0
0
0
0
P2NStsSId_Lo_Lo
R
Port2_Neighbor_Status_Recv_SrcID[15:0]
Power-up Defaults
0
0
0
0
0
0
0
9
0
8
0
7
0
6
0
5
Mnemonic
type offset bits 15
0x90
14
0
13
0
12
0
11
10
P2NStsSId_Lo_Hi
R
Port2_Neighbor_Status_Recv_SrcID[31:16]
Power-up Defaults
0
0
0
0
9
0
8
0
7
0
6
0
5
0
4
Mnemonic
type offset bits 15
0x92
14
0
13
0
12
0
11
10
P2NStsSId_Hi_Lo
R
Port2_Neighbor_Status_Recv_SrcID[47:32]
Power-up Defaults
0
0
0
0
0
0
0
0
0
The Port 2 Link/Neighbor Status Receive Source ID register is comprised of three 16- bit
registers. It contains the source MAC address of the last Link/Neighbor Status frame that
was received on port 2. Reads may be performed in any order.
9.2.33 Ring Supervisor MAC ID Register
Mnemonic
type offset bits 15
0x94
14
13
12
11
0
10
9
8
7
6
5
0
5
4
0
4
0
4
0
3
0
3
0
3
0
2
0
2
0
2
0
1
0
1
0
1
0
0
0
0
0
0
0
RngSprvsrId_Lo_Lo
R
Ring_Supervisor_MacId[15:0]
Power-up Defaults
0
0
0
0
0
0
9
0
8
0
7
0
6
Mnemonic
type offset bits 15
0x96
14
0
13
0
12
0
11
0
10
RngSprvsrId_Lo_Hi
R
Ring_Supervisor_MacId[31:16]
Power-up Defaults
0
0
0
9
0
8
0
7
0
6
0
5
Mnemonic
type offset bits 15
0x98
14
0
13
0
12
0
11
0
10
RngSprvsrId_Hi_Lo
R
Ring_Supervisor_MacId[47:32]
Power-up Defaults
0
0
0
0
0
0
0
75
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