fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
The Ring Supervisor MAC ID register is comprised of three 16- bit registers. It contains
the source MAC address of active ring supervisor. This register must be set to the proper
value in both ring supervisor and non-supervisor modes of operation, for the ring logic to
function correctly. For example to load MAC address 00-11-22-33-44-55, 0x0011 should
be written to RngSprvsrId_Hi_Lo, 0x2233 should be written to RngSprvsrId _Lo_Hi, and
0x4455 should be written to RngSprvsrId _Lo_Lo. Reads and writes may be performed in
any order.
9.2.34 Interface and Media Counters Registers
Mnemonic
type offset bits 15
0x9C
14
13
12
11
10
9
8
7
6
5
4
0
4
0
4
0
4
0
4
0
4
0
4
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
2
0
2
0
2
0
2
0
2
0
2
0
2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P1RxGrpFrmCnt
R
Port1_Group_Frame_Recv_Count[15:0]
Power-up Defaults
0
0
0
0
0
0
0
9
0
8
0
7
0
6
0
5
Mnemonic
type offset bits 15
0x9E
14
0
13
0
12
0
11
0
10
P2RxGrpFrmCnt
R
Port2_Group_Frame_Recv_Count[15:0]
Power-up Defaults
0
0
0
9
0
8
0
7
0
6
0
5
Mnemonic
type offset bits 15
0xA0
14
0
13
0
12
0
11
0
10
P1RxUniFrmCnt
R
Port1_Unicast_Frame_Recv_Count[15:0]
Power-up Defaults
0
0
0
9
0
8
0
7
0
6
0
5
Mnemonic
type offset bits 15
0xA2
14
0
13
0
12
0
11
0
10
P2RxUniFrmCnt
R
Port1_Unicast_Frame_Recv_Count[15:0]
Power-up Defaults
0
0
0
9
0
8
0
7
0
6
0
5
Mnemonic
type offset bits 15
0xA4
14
0
13
0
12
0
11
0
10
P1RxBytCnt_Lo
R
Port1_Recv_Byte_Count[15:0]
Power-up Defaults
0
0
0
9
0
8
0
7
0
6
0
5
Mnemonic
type offset bits 15
0xA6
Power-up Defaults
14
0
13
0
12
0
11
0
10
P1RxBytCnt_Hi
R
Port1_Recv_Byte_Count[31:16]
0
0
0
9
0
8
0
7
0
6
0
5
Mnemonic
type offset bits 15
0xA8
14
0
13
0
12
0
11
0
10
P2RxBytCnt_Lo
R
Port2_Recv_Byte_Count[15:0]
Power-up Defaults
0
0
0
0
0
0
0
76
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