fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
Pin
Signal Name
Type
BGA Pin Descriptions
L3 p2_txen
K4 p2_txer
M3 p2_txd[0]
L4 p2_txd[1]
M4 p2_txd[2]
J4 vcck
output port 2 mii, transmit enable to PHY
output port 2 mii, transmit error to PHY
output port 2 mii, transmit data bit 0 to PHY
output port 2 mii, transmit data bit 1 to PHY
output port 2 mii, transmit data bit 2 to PHY
power 1.8 V digital core supply voltage
ground digital core ground
G6 gndk
H5 gndio
ground i/o ground
H3 vcc3io
power 3.3 V i/o supply voltage
L5 p2_txd[3]
M5 p2_rxc
M6 p2_rxdv
L6 p2_rxer
J9 gndio
output port 2 mii, transmit data bit 3 to PHY
input
input
input
port 2 mii, receive clock from PHY
port 2 mii, receive data valid from PHY
port 2 mii, receive data error from PHY
ground i/o ground
K6 vcc3io
power 3.3 V i/o supply voltage
M7 p2_rxd[0]
L7 p2_rxd[1]
M8 p2_rxd[2]
L8 p2_rxd[3]
M9 p2_col
L9 p2_crs
input
input
input
input
input
input
port 2 mii, receive data bit 0 from PHY
port 2 mii, receive data bit 1 from PHY
port 2 mii, receive data bit 2 from PHY
port 2 mii, receive data, bit 3 from PHY
port 2 mii, collision from PHY
port 2 mii, carrier sense from PHY
K7 vcc3io
H8 gndio
power 3.3 V i/o supply voltage
ground i/o ground
H6 gndk
K5 vcck
ground digital core ground
power 1.8 V digital core supply voltage
M10 p2_lnk_stts
M11 p2_led_grn
L10 p2_led_ylw
M12 reset_n
L11 sys_clk
K10 test
L12 cpu_txen
J10 vcc18a_pll
H10 gnda_pll
K11 cpu_txer
J11 cpu_txc
K12 cpu_txd[0]
K9 vcck
input
port 2 mii, link status from PHY (1:link pass, 0:link fail)
output port 2 mii,, green led
output port 2 mii,, yellow led
input
input
input
input
power 1.8 V analog supply voltage
ground analog ground
input
output cpu mii, 25 MHz transmit clock to CPU
input cpu mii, transmit data bit 0 from CPU
chip reset, active low (internal pull-up)
25 MHz system clock
test, active high (internal pull-down)
cpu mii, transmit enable from CPU
cpu mii, transmit error from CPU
power 1.8 V digital core supply voltage
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