fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588
Data Sheet
April 10, 2013
4.2 BGA Pin Listing
Table 2 BGA Pin List
Pin
Signal Name
Type
BGA Pin Descriptions
C3 sw_event_irq_n output switch event IRQ, must be connected to a high priority
IRQ pin on cpu
B2 ts_event_irq_n output time sync event IRQ. Optional for non-1588 devices.
A1 pps_sig
C2 event_1_sig
B1 event_2_sig
D2 p1_txc
output pulse per second signal for 1588 compliance
input
input
input
external event 1 snapshot trigger from CPU/others
external event 2 snapshot trigger from CPU/others
port 1 mii, transmit clock from PHY
E3 vcck
E6 gndk
power 1.8 V digital core supply voltage
ground digital core ground
F5 gndio
ground i/o ground
F3 vcc3io
power 3.3 V i/o supply voltage
C1 p1_txen
D1 p1_txer
E2 p1_txd[0]
E1 p1_txd[1]
F2 p1_txd[2]
F1 p1_txd[3]
G1 p1_rxc
G2 p1_rxdv
H1 p1_rxer
H2 p1_rxd[0]
J1 p1_rxd[1]
K1 p1_rxd[2]
G3 vcc3io
output port 1 mii, transmit enable to PHY
output port 1 mii, transmit error to PHY
output port 1 mii, transmit data bit 0 to PHY
output port 1 mii, transmit data bit 1 to PHY
output port 1 mii, transmit data bit 2 to PHY
output port 1 mii, transmit data bit 3 to PHY
input
input
input
input
input
input
port 1 mii, receive clock from PHY
port 1 mii, receive data valid from PHY
port 1 mii, receive data error from PHY
port 1 mii, receive data bit 0 from PHY
port 1 mii, receive data bit 1 from PHY
port 1 mii, receive data bit 2 from PHY
power 3.3 V i/o supply voltage
ground i/o ground
G5 gndio
F6 gndk
J3 vcck
ground digital core ground
power 1.8 V digital core supply voltage
J2 p1_rxd[3]
L1 p1_col
K2 p1_crs
M1 p1_lnk_stts
L2 p1_led_grn
K3 p1_led_ylw
M2 p2_txc
input
input
input
input
port 1 mii, receive data bit 3 from PHY
port 1 mii, collision from PHY
port 1 mii, carrier sense from PHY
port 1 mii, link status from PHY (1:link pass, 0:link fail)
output port 1 mii,, green led
output port 1 mii,, yellow led
input
port 2 mii, transmit clock from PHY
32
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