IA186EB/IA188EB
Data Sheet
8-Bit/16-Bit Microcontrollers
July 10, 2011
Table 7. IA186EB Pin/Signal Descriptions (Continued)
Pin
Signal
t1out
Description
Name
t1out
PLCC
47
LQFP
34
PQFP
77
timer 1 output. Output. Depending on the
Timer Mode programmed for Timer 1, this
output can provide a single clock or a
continuous waveform.
test_n
test_n/busy
14
3
46
test. Input. Active Low. When the test_n
input is high (i.e., not asserted), it causes the
IA186EB to suspend operation during the
execution of the WAIT instruction. Operation
resumes when the pin is sampled low
(asserted).
txd0
txd1
txd0
p2.1/txd1
ucs_n
52
58
30
39
45
18
2
8
Transmit (tx) data, Serial Port 0. Output. This
pin is the serial data output for Serial Port 0.
During synchronous serial communications,
txd0 becomes the transmit clock (rxd0
functions as an output for data transmission).
Transmit (tx) data, Serial Port 1. Output. This
pin is the serial data output for Serial Port 1.
During synchronous serial communications,
txd1 becomes the transmit clock (rxd1
functions as an output for data transmission).
ucs_n
61
upper chip select. Output. Active Low. This
pin provides a chip select signal that will be
asserted (low) whenever the address of a
memory bus cycle is within the address space
programmed for that output.
vcc
vss
vcc
vss
1, 23, 11, 29, 13, 34, Power (vcc). This pin provides power for the
42, 64 50, 71 54, 72 IA186EB device. It must be connected to a
+5V DC power source.
2, 22, 10, 30, 12, 14, Ground (vss). This pin provides the digital
43, 63, 49, 51, 33, 35, ground (0V) for the IA186EB. It must be
65, 84 70, 72 53, 73 connected to a vss board plane.
wr_n
wr_n
5
74
37
write. Output. Active Low. When asserted
(low), wr_n indicates that data available on the
data bus are to be latched into the accessed
memory or I/O device.
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