IA186EB/IA188EB
Data Sheet
8-Bit/16-Bit Microcontrollers
July 10, 2011
Table 7. IA186EB Pin/Signal Descriptions (Continued)
Pin
Signal
inta1_n
Description
Name
int3/inta1_n
PLCC
34
LQFP
22
PQFP
65
interrupt acknowledge 1. Input/Output. Active
Low. This pin provides an interrupt
acknowledge handshake in response to an
interrupt request on the int1 pin (see previous
table entry).
lcs_n
lcs_n
29
15
17
4
60
47
lower chip select. Output. Active Low. This
pin provides a chip select signal that will be
asserted (low) whenever the address of a
memory bus cycle is within the address space
programmed for that output.
lock. Output. Active Low. When asserted
(low), this signal indicates that the bus cycle in
progress is cannot be interrupted. While
lock_n is active, the IA186EB will not service
bus requests such as HOLD.
lock_n
lock_n
ncs_n
nmi
ncs_n
nmi
60
17
NA
5
NA
48
numerics coprocessor select. Output. Active
Low. This signal is asserted (low) when the
IA186EB accesses an Intel 80C187 Numerics
Coprocessor.
non-maskable interrupt. Input. Active High.
When the nmi signal is asserted (high) it
causes a Type 2 interrupt to be serviced by the
IA186EB.
Note: The assertion of nmi is latched internally
by the IA186EB.
once_n
a19/once_n
83
69
32
on-circuit emulation. Input. Active Low. Note:
ONCE Mode is used for device testing.
If the once_n pin is driven low during a reset
operation, all IA186EB output and input/output
pins are placed in a high-impedance state.
This pin is weakly held high while resin_n is
active.
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