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EG80C188EB25 参数 Datasheet PDF下载

EG80C188EB25图片预览
型号: EG80C188EB25
PDF下载: 下载PDF文件 查看货源
内容描述: 8位/ 16位微控制器 [8-Bit/16-Bit Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 85 页 / 1257 K
品牌: INNOVASIC [ INNOVASIC, INC ]
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IA186EB/IA188EB  
Data Sheet  
8-Bit/16-Bit Microcontrollers  
July 10, 2011  
Table 8. IA188EB Pin/Signal Descriptions (Continued)  
Pin  
Signal  
bclk1  
Name  
p2.2/bclk1  
PLCC  
59  
LQFP  
46  
PQFP  
9
Description  
baud clock, Serial Port 1. Input. The bclk1 pin  
can be used to provide an alternate clock  
source for Serial Port 1. The input clock rate  
cannot be greater than one-half the operating  
frequency of the IA188EB.  
clkin  
clkin  
41  
28  
71  
clock input. Input. The clkin pin is the input  
connection for an external clock. An external  
oscillator, operating at two times the required  
processor operating frequency, can be  
connected to this pin.  
If a crystal is used to supply the clock, it is  
connected between the clkin pin and the  
oscout pin (see oscout table entry). When a  
crystal is connected, it drives an internal Pierce  
oscillator to the IA188EB.  
clkout  
clkout  
44  
31  
74  
clock output. Output. The clkout pin provides  
a timing reference for inputs and outputs of the  
IA188EB. This clock output is one-half the input  
clock (clkin) frequency. The clkout signal has  
a 50% duty cycle, transitioning every falling  
edge of clkin.  
cts0_n  
cts1_n  
den_n  
dt/r_n  
cts0_n  
p2.4/cts1_n  
den_n  
51  
56  
11  
16  
38  
43  
80  
NA  
1
6
clear to send, Serial Port 0. Input. Active Low.  
When this input is high (i.e., not asserted), data  
transmission from Serial Port 0 is inhibited.  
When the signal is asserted (low), data  
transmission is permitted.  
clear to send, Serial Port 1. Input. Active Low.  
When this input is high (i.e., not asserted), data  
transmission from Serial Port 1 is inhibited.  
When the signal is asserted (low), data  
transmission is permitted.  
data enable. Output. Active Low. This signal  
is used to enable of bidirectional transceivers in  
a buffered system. The den_n signal is  
asserted (low) only when data are to be  
transferred on the bus.  
data transmit/receive. Output. This signal is  
used to control the direction of data flow for  
bidirectional buffers in a buffered system.  
When dt/r_n is high, the direction indicated is  
transmit; when dt/t_n is low, the direction  
indicated is receive.  
43  
NA  
dt/r_n  
IA211080314-13  
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