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EG80C188EB25 参数 Datasheet PDF下载

EG80C188EB25图片预览
型号: EG80C188EB25
PDF下载: 下载PDF文件 查看货源
内容描述: 8位/ 16位微控制器 [8-Bit/16-Bit Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 85 页 / 1257 K
品牌: INNOVASIC [ INNOVASIC, INC ]
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IA186EB/IA188EB  
Data Sheet  
8-Bit/16-Bit Microcontrollers  
July 10, 2011  
2.3  
IA188EB Pin/Signal Descriptions  
Descriptions of the pin and signal functions for the IA188EB microcontroller are provided in  
Table 8.  
Several of the IA188EB pins have different functions depending on the operating mode of the  
device. Each of the different signals supported by a pin is listed and defined in Table 8—  
indexed alphabetically in the first column of the table. Additionally, the name of the pin  
associated with the signal as well as the pin numbers for the PLCC, LQFP, and LQFP packages  
are provided in the ―Pin‖ column.  
Table 8. IA188EB Pin/Signal Descriptions  
Pin  
Signal  
a8  
a9  
Name  
a8  
a9  
a10  
a11  
a12  
a13  
a14  
a15  
PLCC  
62  
67  
69  
71  
73  
75  
77  
79  
80  
81  
82  
83  
61  
66  
68  
70  
72  
74  
76  
78  
6
LQFP  
48  
53  
55  
57  
59  
61  
63  
65  
66  
67  
68  
69  
47  
52  
54  
56  
58  
60  
62  
64  
75  
PQFP  
11  
16  
18  
20  
22  
24  
26  
28  
29  
30  
31  
32  
10  
15  
17  
19  
21  
23  
25  
27  
38  
Description  
address Bits [8-19]. Output. These pins  
provide the 12 most-significant bits of the  
Address Bus. During the entire IA188EB bus  
cycle, Address Bits [819] are presented on the  
bus and can be latched using the ale signal  
(see table entry).  
a10  
a11  
a12  
a13  
a14  
a15  
a16  
a17  
a18  
a19  
ad0  
ad1  
ad2  
ad3  
ad4  
ad5  
ad6  
ad7  
ale  
a16  
a17  
a18  
a19/once_n  
ad0  
address/data Bits [07]. Input/Output. These  
pins provide a multiplexed Address Bus and  
Data Bus. During the address portion of the  
IA188EB bus cycle, Address Bits [07] are  
presented on the bus and can be latched using  
the ale signal (see next table entry). During the  
data portion of the IA188EB bus cycle, 8-bit  
data are present on these lines.  
ad1  
ad2  
ad3  
ad4  
ad5  
ad6  
ad7  
ale  
address latch enable. Output. Active High.  
This signal is used to latch the address  
information during the address portion of a bus  
cycle.  
bclk0  
p2.5/bclk0  
54  
41  
4
baud clock, Serial Port 0. Input. The bclk0 pin  
can be used to provide an alternate clock  
source for Serial Port 0. The input clock rate  
cannot be greater than one-half the operating  
frequency of the IA188EB.  
IA211080314-13  
UNCONTROLLED WHEN PRINTED OR COPIED  
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