IA186XL/IA188XL
16-Bit Microcontrollers
Data Sheet
July 6, 2011
Table 8. IA188XL Pin/Signal Descriptions (Continued)
Pin
Signal
ale
Name
ale/qs0
PLCC
61
PQFP
10
LQFP
29
Description
address latch enable. Output. Active High.
This signal is used to latch address
information during the address portion of a
bus cycle.
ardy
ardy
55
56
20
19
37
36
asynchronous ready. Input. Indicates to the
processor the addressed memory space or i/o
device will complete the transfer.
clock output. Output. The clkout pin
provides a timing reference for inputs and
outputs of the IA188XL. This clock output is
one-half the input clock (clkin) frequency.
The clkout signal has a 50% duty cycle,
transitioning every falling edge of clkin.
clkout
clkout
den_n
den_n
39
38
56
data enable. Output. Active Low. This signal
is used to enable bidirectional transceivers in
a buffered system. The den_n signal is
asserted (low) only when data are to be
transferred on the bus.
drq0
drq1
drq0
drq1
18
19
61
60
79
78
dma request 0 or 1. Input. Asserted high by
an external device to request DMA Channel 0
or 1 to perform a transfer. These signals are
level-triggered and internally synchronized
dt/r_n
dt/r_n
40
37
54
data transmit/receive. Output. This signal is
used to control the direction of data flow for
bidirectional buffers in a buffered system.
When dt/r_n is high, the direction indicated is
transmit; when dt/r_n is low, the direction
indicated is receive.
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