IA186XL/IA188XL
16-Bit Microcontrollers
Data Sheet
July 6, 2011
Table 7. IA186XL Pin/Signal Descriptions (Continued)
Pin
Signal
qs0
Name
ale/qs0
PLCC
61
PQFP
10
LQFP
29
Description
queue status 0, queue status 1. Output.
qs1
wr_n/qs1
63
8
27
QS1 QS0
0
0
0
1
No Queue operations
First byte of opcode pulled from
Queue
1
1
Additional bytes pulled from
Queue
1
0
Queue is flushed
qsmd_n
rd_n
rd_n/qsmd_n
rd_n/qsmd_n
62
62
9
9
28
28
queue status mode. Input. Sampled at reset.
read. output. Active Low. When asserted
(low), rd_n indicates that the accessed
memory or I/O device must drive data from the
location being accessed onto the data bus.
res_n
reset
res_n
reset
24
57
55
18
73
34
res_n. Input. Forces the processor to
terminate present activity, reset the internal
logic, and enter a dormant state until res_n
goes high.
reset is an output signal indicating the CPU is
being reset. It can be used as a system reset.
s0_n
s1_n
s2_n
s0_n
s1_n
s2_n
52
53
54
23
22
21
40
39
38
status [2:0]_n are outputs. During a bus
cycle, the status (i.e., type) of cycle is encoded
on these lines as follows:
s2_n s1_n s0_n Bus Cycle Status
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt Acknowledge
Read I/O
Write I/O
Processor HALT
Queue Instruction Fetch
Read Memory
Write Memory
No Bus Activity
s3
s4
s5
s6
a16/s3
a17/s4
a18/s5
a19/s6
68
67
66
65
3
4
5
6
21
22
23
24
status [6:3] are Outputs.
Bus Cycle A19/s6 A18/s5 A17/s4 A16/s3
T1
T2
T3
Tw
T4
A19
N
N
N
N
A18
0
0
0
0
A17
0
0
0
0
A16
0
0
0
0
____________
N = 0 for CPU bus cycle.
N = 1 for DMA or refresh cycle.
srdy
srdy
49
27
44
synchronous ready. Input.
®
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