IA186XL/IA188XL
16-Bit Microcontrollers
Data Sheet
July 6, 2011
Table 8. IA188XL Pin/Signal Descriptions (Continued)
Pin
Signal
res_n
Name
res_n
PLCC
24
PQFP
55
LQFP
73
Description
res_n. Input. Forces the processor to
terminate its present activity, reset the internal
logic, and enter a dormant state until res_n
goes high.
reset
reset
57
64
18
7
34
26
reset is an output signal indicating the CPU is
being reset. It can be used as a system reset.
refresh. Output. rfsh_n is asserted low to
rfsh_n
rfsh_n
indicate a refresh bus cycle.
s0_n
s1_n
s2_n
s0_n
s1_n
s2_n
52
53
54
23
22
21
40
39
38
status [2:0]_n are outputs. During a bus cycle
the status (i.e., type) of cycle is encoded on
these lines as follows:
s2_n s1_n s0_n Bus Cycle Status
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt Acknowledge
Read I/O
Write I/O
Processor HALT
Queue Instruction Fetch
Read Memory
Write Memory
No Bus Activity
s3
s4
s5
s6
a16/s3
a17/s4
a18/s5
a19/s6
68
67
66
65
3
4
5
6
21
22
23
24
status [6:3] are outputs.
Bus Cycle A19/s6 A18/s5 A17/s4 A16/s3
T1
T2
T3
Tw
T4
A19
N
N
N
N
A18
0
0
0
0
A17
0
0
0
0
A16
0
0
0
0
____________
N = 0 for CPU bus cycle.
N = 1 for DMA or refresh cycle.
srdy
test_n
srdy
test_n/busy
49
47
27
29
44
46
synchronous ready. Input.
test. Input. Active Low. When the test_n
input is high (i.e., not asserted), it causes the
IA188XL to suspend operation during the
execution of the WAIT instruction. Operation
resumes when the pin is sampled low
(asserted).
tmr in 0
tmr in 1
tmr in 0
tmr in 1
20
21
59
58
77
76
timer 0 input. Input. Depending on the Timer
Mode programmed for Timer 0, this input is
used either as clock input or a control signal.
timer 1 input. Input. Depending on the Timer
Mode programmed for Timer 1, this input is
used either as clock input or a control signal.
®
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