IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
acknowledge cycle timing. Figure 19 presents the software halt cycle. Table 89 presents the
software halt cycle timing. Figure 20 presents the clock—active mode. Figure 21 presents the
clock—power-save mode. Table 90 presents the clock timing.
Figure 22 presents the srdy—synchronous ready. Figure 23 presents the ardy—asynchronous
ready. Figure 24 presents the peripherals. Table 91 presents the ready and peripheral timing.
Figures 25 and 26 present Reset 1 and Reset 2, respectively. Figures 27 and 28 present the bus
hold entering and bus hold leaving, respectively. Table 92 presents the reset and bus hold
timing.
Figure 29 presents the synchronous serial interface. Table 93 presents the synchronous serial
interface timing.
Table 80. AC Characteristics Over Commercial Operating Ranges (40 MHz)
No.
Name
Description
Min
Max
General Timing Requirements
1
2
tDVCL
tCLDX
Data in Setup
Data in Hold
10
0
–
–
General Timing Responses
3
4
5
6
8
9
tCHSV
tCLSH
tCLAV
tCLAX
tCHDX
tCHLH
Status Active Delay
Status Inactive Delay
ad Address Valid Delay
Address Hold
Status Hold Time
0
0
0
0
0
0
6
6
12
12
–
ale Active Delay
8
10 tLHLL
ale Width
tCLCH-5
–
11 tCHLL
12 tAVLL
13 tLLAX
14 tAVCH
15 tCLAZ
16 tCLCSV
17 tCXCSX
18 tCHCSX
19 tDXDL
20 tCVCTV
21 tCVDEX
22 tCHCTV
23 tLHAV
80 tCLCLX
81 tCLCSL
82 tCLRF
84 tLRLL
ale Inactive Delay
0
8
–
–
–
12
12
–
12
–
10
0
10
–
ad Address Valid to ale Low
ad Address Hold from ale Inactive
ad Address Valid to Clock High
ad Address Float Delay
mcs_n/pcs_n Inactive Delay
mcs_n/pcs_n Hold from Command Inactive
mcs_n/pcs_n Inactive Delay
den_n Inactive to dt/r_n Low
Control Active Delay 1
den_n Inactive Delay
Control Active Delay 2
ale High to Address Valid
lcs_n Inactive Delay
lcs_n Active Delay
clkouta High to rfsh_n Invalid
lcs_n Precharge Pulse Width
tCLCH
tCHCL
0
0
0
tCLCH
0
0
0
0
0
7.5
0
0
9
9
12
–
0
tCLCL + tCLCH
®
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