IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
Table 77. Synchronous Serial Transmit Registers
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
SD7–SD0
Bits [15–8]—Reserved.
Bits [7–0]—SD7–SD0 → Data to be transmitted over the SDATA pin.
5.1.56 SSC (012h)
Synchronous Serial Control Register. This register controls the operation of the sden1 and sden0
outputs and the baud rate of the SSI port. The sden1 and sden0 outputs are held high when the
respective bit is set to 1, but in the event that both DE1 and DE0 are set to 1 then only sden0 will
be held high. The value of the SSR register is 0000h at reset (see Table 78).
Table 78. Synchronous Serial Control Registers
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
SCLKDIV Reserved DE1 DE0
Bits [15–6]—Reserved.
Bits [5–4]—SCLKDIV SCLK Divide → These bits set the SCLK frequency. SCLK is
the result of dividing the internal processor clock by 2, 4, 8, or 16 as shown below.
SCLKDIV SCLK Frequency Divider
00b
01b
10b
11b
Processor Clock/2
Processor Clock/4
Processor Clock/8
Processor Clock/16
Bits [3–2]—Reserved.
Bit [1]—DE1 SDEN1 → The SDEN1 bit is held high when this bit is set to 1 and SDEN1
is held low when this bit is set to 0.
Bit [0]—DE0 SDEN0 → The SDEN0 bit is held high when this bit is set to 1 and SDEN0
is held low when this bit is set to 0.
5.1.57 SSS (010h)
Synchronous Serial Status Register. This is a read-only register that indicates the state of the SSI
port. The value of the SSR register is 0000h at reset (see Table 79).
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