IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
Bits [15–3]—Reserved → Write as 0.
Bits [2–0]—L2–L0 Interrupt Type → The priority or the IS (interrupt service) bit to be
reset is encoded in these three bits. Writing to these bits caused the issuance of an EOI
for the interrupt type (see Table 14, Interrupt Types).
5.1.53 INTVEC (020h) Interrupt Vector Register (Slave Mode)
The CPU shifts left 2 bits (multiplies by 4) an 8-bit interrupt type, generated by the interrupt
controller, to produce an offset into the interrupt vector table. The INTVEC register is undefined
at reset (see Table 75).
Table 75. Interrupt Vector Register
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
T4–T0
Reserved
Bits [15–8]—Reserved → Read as 0.
Bits [7–3]—T4–T0 Interrupt Type → These five bits contain the five most significant bits
of the interrupt types used for the internal interrupt type. The least significant three bits
of the interrupt type are supplied by the interrupt controller, as set by the priority level of
the interrupt request.
Bits [2–0]—Reserved → Read as 0.
5.1.54 SSR (018h)
Synchronous Serial Receive Register. This register holds the serial data received on the SSI
port. The value of the SSR register is undefined at reset (see Table 76).
Table 76. Synchronous Serial Receive Register
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
SR7-SR0
Bits [15–8]—Reserved.
Bits [7–0]—SR7–SR0 → Data received over the SDATA pin.
5.1.55 SSD0 (016h) and SSD0 (014h)
Synchronous Serial Transmit Registers. These registers hold the data to be transmitted by the
SSI ports. The value of these registers is undefined at reset (see Table 77).
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