IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
Table 72. Poll Register
15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
IREQ
Reserved
S4–S0
Bit [15]—IREQ Interrupt Request → This bit is set to 1 when an interrupt is pending.
During this state, the S4–S0 bits contain valid data.
Bits [14–5]—Reserved.
Bits [4–0]—S4–S0 Poll Status → These bits show the interrupt type of the highest
priority pending interrupt.
5.1.51 EOI (022h) End-Of-Interrupt Register (Master Mode)
The In Service flags of the In-Service register are reset when a write is made to the EOI register.
The interrupt service routine (ISR) should write to the EOI to reset the IS bit, in the In-Service
register, for the interrupt before executing an IRET instruction that ends an interrupt service
routine. Because it is most secure, the specific EOI reset is the preferred method for resetting the
IS bits. The EOI register is write-only (see Table 73).
Table 73. End-of-Interrupt Register
15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
NSPEC
Reserved
S4–S0
Bit [15]—NSPEQ Non-Specific EOI → When set to 1, this bit is a non-specific EOI.
When 0, it indicates the specific EOI.
Bits [14–5]—Reserved.
Bits [4–0]—S4–S0 Source Interrupt Type → These bits show the interrupt type of the
highest priority pending interrupt.
5.1.52 EOI (022h) Specific End-Of-Interrupt Register (Slave Mode)
Specific End-Of-Interrupt Register. An In-Service flag of a specific priority in the In-Service
register, it is reset when a write is made to the EOI register. A three-bit user-supplied priority-
level value that points to the in-service bit that is to be reset. Writing this value to this register
resets the specific bit. The EOI register is write-only and undefined at reset (see Table 74).
Table 74. Specific End-of-Interrupt Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
L2–L0
®
IA211050831-19
UNCONTROLLED WHEN PRINTED OR COPIED
http://www.Innovasic.com
Customer Support:
Page 95 of 146
1-888-824-4184
INNOVASIC [ INNOVASIC, INC ]
