IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
Table 84. Interrupt Acknowledge Cycle Timing
a
a
No.
Name
Description
Min
Max
General Timing Requirements
1
2
tDVCL
tCLDX
Data in Setup
Data in Hold
10
0
–
–
General Timing Responses
3
4
5
9
tCHSV
tCLSH
tCLAV
tCHLH
Status Active Delay
0
0
0
0
6
6
12
8
Status Inactive Delay
ad Address Valid Delay
ale Active Delay
10 tLHLL
11 tCHLL
19 tDXDL
22 tCHCTV
68 tCHAV
ale Width
ale Inactive Delay
den_n Inactive to dt/r_n Low
Control Active Delay 2
clkouta High to a Address Valid
tCLCH-5
–
8
–
10
8
0
0
0
0
a
In nanoseconds.
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