IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
0ns
20ns
40ns
60ns
80ns
100ns
120ns
28
140ns
160ns
180ns
CLK0
clk0
19-a0
Address
a19–a0
9
11
ale
ale
27
10
26
rd_n
rd_n
80
25
27
81
lcs_n
79
82
85
rfsh_
rfsh_n
86
Figure 18. PSRAM Refresh Cycle
Table 83. PSRAM Refresh Cycle Timing
a
a
No.
Name
Description
Min
Max
General Timing Requirements
1
2
tDVCL
tCLDX
Data in Setup
Data in Hold
10
0
–
–
General Timing Responses
9
tCHLH
ale Active Delay
ale Width
ale Inactive Delay
0
8
–
8
10 tLHLL
11 tCHLL
tCLCH-5
0
Read/Write Cycle Timing Responses
25 tCLRL
26 tRLRH
27 tCLRH
28 tRHLH
80 tCLCLX
81 tCLCSL
rd_n Active Delay
rd_n Pulse Width
rd_n Inactive Delay
rd_n Inactive to ale High
lcs_n Inactive Delay
lcs_n Active Delay
0
10
–
10
–
9
9
tCLCL
0
tCLCH
0
0
Refresh Cycle Timing Responses
79 tCHRFD
82 tCLRF
85 tRFCY
86 tLCRF
clkouta High to rfsh_n Valid
clkouta High to rfsh_n Invalid
rfsh_n Cycle Time
0
0
12
12
–
6tCLCL
2tCLCL
lcs_n Inactive to rfsh_n Active Delay
–
a
In nanoseconds.
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IA211050902-19
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