IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
these registers must be adjusted to reflect the new processor clock frequency if power-save mode
is in effect. The baud rate divisor may be calculated from:
BAUDDIV = (Processor Frequency/(32 x baud rate)) -1
(Equation 1)
By setting the BAUDDIV to 0000h, the maximum baud rate of 1/32 of the internal processor
frequency clock is set. Setting BAUDDIV to 129 (81h) provides a baud rate of 9600 at 40 MHz.
The baud rate tolerance is +4.6% to –1.9% with respect to the actual serial port baud rate, not the
target baud rate (see Table 35).
Table 35. Baud Rates
Divisor Based on CPU Clock Rate
Baud Rate
300
600
1200
2400
4800
9600
14400
20 MHz 25 MHz 33 MHz 40 MHz
4166
2083
1041
520
260
130
42
5208
2604
1302
651
325
162
53
6875
3437
1718
859
429
214
71
8333
4166
2083
1041
520
260
85
19200
31
39
53
64
625 Kbaud
781.25 Kbaud
1.041 Mbaud
1.25 Mbaud
0
NA
NA
NA
NA
0
NA
NA
NA
NA
0
NA
1
NA
NA
0
The value of the SPBAUD register at reset is undefined (see Table 36).
Table 36. Serial Port Baud Rate Divisor Registers
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
BAUDDIV
Bits [15–0]—BAUDDIV Baud Rate Divisor → Defines the divisor for the internal
processor clock.
5.1.20 SPRD (086h)
Serial Port Receive Data Register. Data received over the serial port are stored in this register
until read. The data are received initially by the receive shift register (no software access)
permitting data to be received while the previous data are being read.
The RDR bit (Receive Data Ready) in the serial port status register indicates the status of the
SPRD register. Setting the RDR bit to 1 indicates there is valid data in the receive register. The
value of the SPRD register is undefined at reset (see Table 37).
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