欢迎访问ic37.com |
会员登录 免费注册
发布采购

AM186EM-25VIW 参数 Datasheet PDF下载

AM186EM-25VIW图片预览
型号: AM186EM-25VIW
PDF下载: 下载PDF文件 查看货源
内容描述: 8位/ 16位微控制器 [8-Bit/16-Bit Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 146 页 / 1574 K
品牌: INNOVASIC [ INNOVASIC, INC ]
 浏览型号AM186EM-25VIW的Datasheet PDF文件第72页浏览型号AM186EM-25VIW的Datasheet PDF文件第73页浏览型号AM186EM-25VIW的Datasheet PDF文件第74页浏览型号AM186EM-25VIW的Datasheet PDF文件第75页浏览型号AM186EM-25VIW的Datasheet PDF文件第77页浏览型号AM186EM-25VIW的Datasheet PDF文件第78页浏览型号AM186EM-25VIW的Datasheet PDF文件第79页浏览型号AM186EM-25VIW的Datasheet PDF文件第80页  
IA186EM/IA188EM  
Data Sheet  
8-Bit/16-Bit Microcontrollers  
February 25, 2011  
Bit [10]RXIE Receive Data Ready Interrupt Enable This bit enables the generation  
of an interrupt request whenever the receive register contains valid data (RDR Bit [1]).  
The respective port does not generate interrupts when this bit is 0. Interrupts continue to  
be generated as long as RDR and the RXIE are 1.  
Bit [9]LOOP Loop Back The serial port is placed into the loop-back mode when  
this bit is set.  
Bit [8]BRK Send Break When this bit is set to 1, the txd pin is driven low,  
overriding any data that may be in the course of being shifted out of the transmit shift  
register.  
Note: See the definitions of long and short break in Section 5.1.2, SPSTS  
(Serial Port Status Register).  
Bit [7]BRKVAL Break Value This is the ninth data bit transmitted when in modes 2  
and 3. This bit is cleared at each transmitted word and is not buffered. To transmit data  
with this bit set high, the following procedure is recommended.  
1. The TEMT bit in the serial port status register must go high.  
2. Set the TB8 bit by writing it to the serial port control register.  
3. Write the transmit character to the serial port transmit register.  
Serial port 0 is a special case. If this bit is 1, the associated pins are used for flow  
control overriding the Peripheral Chip Select signals. This bit is 0 at reset.  
Bits [65]PMODE Parity Mode When this bit is set to 1, the txd pin is driven low,  
overriding any data that may be in the course of being shifted out of the transmit shift  
register.  
Note: See the definitions of long and short break in Section 5.1.2, SPSTS  
(Serial Port Status Register).  
Bit [4]WLGN Word Length The number of bits transmitted or received in a frame is  
determined by the value of this bit. When this bit is 1, the number of data bits in a frame  
is 8. When 0, it is 7. This bit is 0 at reset.  
Bit [3]STP Stop Bits This bit specifies the number of stop bits used to indicate the  
end of a frame. When this bit is 1, the number of stop bits is 2. When 0, it is 1. This bit  
is 0 at reset.  
Bit [2]TMODE Transmit Mode When this bit is 1, the transmit section of the serial  
port is enabled. When 0, it is disabled.  
®
IA211050831-19  
UNCONTROLLED WHEN PRINTED OR COPIED  
http://www.Innovasic.com  
Customer Support:  
Page 76 of 146  
1-888-824-4184  
 复制成功!